Serializer/deserializer (SERDES) circuits are becoming ubiquitous in many computational environments. The SERDES can compress a relatively wide, parallel input into a relatively narrow, serial signal (e.g., a single “bit,” differential signal) for communication over a serial bus. The serial bus switches at an appreciably higher rate than the parallel bus, and serial communication of the data stream tends to reduce cost, complexity, power, and board real estate relative to comparable parallel communications. As bus speeds increase, parallel communications manifest even higher power consumption and more issues relating to timing (e.g., skew mismatches and bit misalignment), making SERDES circuits even more attractive.
Some SERDES applications use phased clocks to reduce power and complexity. For example, four clock signals can be generated by separate clocks at a same nominal frequency, separated from each other by 90-degrees, and combined to effectively generate four times the data rate of any of the clocks individually. However, slight differences between the multiple, separate, phased clocks (e.g., differences in their respective phase-locked loops, manufacturing variance, clock distribution, etc.) can cause deterministic jitter and/or other error in the combined clock output. When four phased clocks are used, the clocks can be considered “quadrature clocks” and the error can be considered as “quadrature error.” or “QE.” For example, when such phased clocks are used for a SERDES transmission clock, particularly at very high data rates, the deterministic jitter (e.g., QE) can appreciably impact link performance.